10
?2007 Semtech Corp.
www.semtech.com
SC2463
POWER MANAGEMENT
Frequency Setting and Synchronization
Frequency Setting and Synchronization
Frequency Setting and Synchronization
Frequency Setting and Synchronization
Frequency Setting and Synchronization
The internal oscillator free-running frequency of the
SC2463 is set by an external resistor using the following
formula:
3
9
freq
10
x
12
fs
10
x
9
.
7
R
=
When it is synchronized externally, the applied clock fre-
quency should be equal or greater than the free-running
frequency.
Setting Current Limit
Setting Current Limit
Setting Current Limit
Setting Current Limit
Setting Current Limit
SC2463 monitors the voltage drop in the lower MOSFETs
Rdson voltage to sense an over current condition. This
method of current sensing minimizes any unnecessary
losses due to external sense resistance.
The SC2463 utilizes an internal current source and an
external resistor connected from the ILIM pins to the
AGND pin to program a current limit level. This limit is
programmable by choosing the resistor relative to the
level required. The value of the resistor can be selected
by the following formula:
)
Rdson
*
IIim
/(
2000
lim
Ri =
Rilim should be between 10K and 100K.
An internal comparator with a reference from the level
set by the external resistor monitors the voltage drop
across the lower MOSFET. Once the Vdson of the MOSFET
exceeds this level, the low side gate is turned on and the
upper MOSFET is turned off in the next switching cycle.
Gate Drives
Gate Drives
Gate Drives
Gate Drives
Gate Drives
The low side gate driver is supplied from PVCC and pro-
vides a peak source/sink current of 1A. The high side
gate drive is also capable of sourcing and sinking peak
currents of 1A. The high side MOSFET gate drive can be
provided by an external 12V supply that is connected
from BST to GND. The actual gate to source voltage of
the upper MOSFET will approximately equal 7V (12V-VCC).
If the external 12V supply is not available, a classical
bootstrap technique can be implemented from the PVCC
supply. A bootstrap capacitor is connected from BST to
Phase while PVCC is connected through a diode (Schottky
or other fast low VF diode) to the BST. This will provide a
gate to source voltage approximately equal to the
VCC-Vdiode drop.
Applications Information
The SC2463 is designed to control and drive two N-Chan-
nel MOSFET PWM synchronous buck switchers and two
positive linear regulators. The two PWM switchers are
synchronized 180?out of phase for low input ripple and
noise. The switching frequency is programmable to opti-
mize design. The SC2463 PWM switchers feature lossless
current sensing and programmable over current limit. The
two positive linear regulators output voltages are adjust-
able.
PP PP Poo oo oww ww wer Supplies
er Supplies
er Supplies
er Supplies
er Supplies
Supplies VIN, PVCC and AVCC from the input source are
used to power the SC2463. An external PNP transistor
linear regulator supplies AVCC and PVCC. The AVCC sup-
ply provides the bias for the oscillator, the switchers, the
linear regulator controllers and the POK circuitry. PVCC is
used to drive the low side MOSFET gate. In low shut-
down current mode, the PNP transistor is turned off, dis-
abling AVCC and PVCC.
Soft-start, Sequencing and Disabling
Soft-start, Sequencing and Disabling
Soft-start, Sequencing and Disabling
Soft-start, Sequencing and Disabling
Soft-start, Sequencing and Disabling
A 10?/SPAN>A current source pulls up on the SS/SHDN pin.
When the SS/SHDN pin reaches 0.5V, the first switcher
is activated and the reference input of the error ampli-
fier is ramped up with the soft-start voltage. When the
SS/SHDN pin reaches 2V, the SS/SHDN pin is pulled
down to approximately 0.7V and the second switcher
begins to soft-start in an identical fashion to the first
switcher. When the SS/SHDN pin reaches 2V for the
second time, the SS/SHDN pin is pulled down to approxi-
mately 0.7V again, and then the positive linear regula-
tors ramp up with the SS/SHDN pin voltage. The SS/
SHDN pin is eventually pulled up to the supply AVCC. The
soft-start time is controlled by the value of the capacitor
connected to the SS/SHDN pin.
If the SS/SHDN pin is pulled down below 0.5V, the
SC2463 is disabled. If the SS/SHDN pin is pulled down
below 0.34V, the bias PNP transistor for SC2463 is dis-
abled and the supply current is only 100uA.
The power-ok circuitry monitors the FB inputs of the
error amplifiers of the switchers. If the voltage on
these inputs goes above 0.55V or below 0.45V then
the POK pin is pulled low. The POK pin is held low until
the end of the start-up sequence.
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